Cadence Design Systems > Case Studies > VIA Telecom's Enhanced Productivity with Cadence Solutions

VIA Telecom's Enhanced Productivity with Cadence Solutions

Technology Category

Networks & Connectivity - LoRa
Networks & Connectivity - Low-Power Wide-Area Network

Applicable Industries

Electrical Grids
Telecommunications

Applicable Functions

Product Research & Development
Quality Assurance

Use Cases

Time Sensitive Networking

Services

System Integration

About The Customer

VIA Telecom is a leading fabless semiconductor company that specializes in developing low-power code division multiple access (CDMA) baseband processors for mobile applications. The company's latest single-chip CDMA baseband processors support a range of dual-mode technologies, including CDMA2000, 1xEVDO, and CDMA2000/GSM. To support its global customer base of handset makers, VIA Telecom maintains International Design Centers around the world. Handsets based on the company’s processors can be found in products in more than 20 countries around the world. Frank Hsu, an ASIC design manager at the company, oversees the methodology for delivering netlists to the back-end team, as well as the timing closure and production test processes.

The Challenge

VIA Telecom, a leading fabless semiconductor company, was facing a significant challenge in delivering low-power baseband processors in a highly competitive market. The company's customers, primarily handset manufacturers, were under increasing pressure to deliver unique mobile devices with low power consumption and long battery life. These customers were also facing shortened design cycles due to time-to-market demands. To keep pace with its customers, VIA Telecom needed to move away from its manual process for verifying the power intent of its digital baseband processor designs. The company was seeking a proven solution with strong support to automate this process and maintain low power consumption while ensuring timely delivery of their products.

The Solution

VIA Telecom turned to Cadence for a solution. The company implemented Cadence Encounter Conformal Low Power, which enabled the engineers to create and validate power intent in the context of their design. This tool merges low-power equivalence checking with structural and functional checks, enabling full-chip verification of power-efficient designs. VIA Telecom also used Cadence Encounter Digital Implementation System for physical implementation of its design and Cadence Encounter RTL Compiler for top-down global register-transfer level (RTL) design synthesis. Additionally, the company used Cadence Incisive Enterprise Simulator for automated testbench creation, low-power and metric-driven verification, and mixed-signal verification. Support from local Cadence applications engineers helped the team adapt the new flow into their legacy process smoothly and efficiently.

Operational Impact

By automating its power verification process with Cadence's solutions, VIA Telecom was able to significantly enhance its productivity. The company reduced the development time for its digital baseband processors by 30%, enabling it to meet the increasingly aggressive product development cycles of its customers. With the same amount of engineering resources, the company was able to take on 25% more projects, opening up opportunities for new business. The company also achieved first silicon success, demonstrating the effectiveness of the implemented solutions. The success with the digital side led VIA Telecom to adapt its Cadence low-power flow to its process for small mixed-signal devices, further enhancing its productivity.

Quantitative Benefit