Cadence Design Systems > Case Studies > Fujitsu and Cadence: Revolutionizing Mobile WiMAX with Power-Optimized Design

Fujitsu and Cadence: Revolutionizing Mobile WiMAX with Power-Optimized Design

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Technology Category
  • Networks & Connectivity - LoRa
  • Networks & Connectivity - MQTT
Applicable Industries
  • Electrical Grids
  • Telecommunications
Applicable Functions
  • Product Research & Development
  • Quality Assurance
Use Cases
  • Time Sensitive Networking
  • Visual Quality Detection
Services
  • System Integration
  • Testing & Certification
About The Customer
Fujitsu Microelectronics Limited is a global leader in microelectronics for computers and communication devices. The company has been at the forefront of developing new technologies to meet the growing bandwidth requirements of mobile phones due to advances in multimedia offerings and consumer demand. Over the past five years, Fujitsu has been instrumental in developing a new standard for Worldwide Interoperability for Microwave Access (WiMAX). The company has successfully developed the first 65nm SoC for mobile WiMAX applications, a fully integrated MAC and PHY mixed-signal baseband processor designed to support frequencies ranging from 2 to 11GHz in both licensed and unlicensed bands.
The Challenge
Fujitsu Microelectronics Limited, a global leader in microelectronics for computers and communication devices, was faced with the challenge of making mobile WiMAX a reality by reducing chip size and power requirements. The key to achieving this was optimizing the power design for the lowest possible overall usage and shutoff leakage. Previously, independent decisions made at each stage of the design process often impacted other areas in unforeseen ways, adversely affecting the final power characteristics. The challenge was further compounded by the need to align power design around CPF with accurate simulation, move to smaller geometries, reduce design time, and improve the quality of silicon.
The Solution
Fujitsu adopted a more unified approach to power design, applying reference specifications from the beginning of the design process to drive optimization across engineering specializations. This approach was enabled by the Common Power Format (CPF)-enabled Cadence® Low-Power methodology, which became an integral part of the reference design flow (RDF) mechanism for low-power, submicron system-on-chip (SoC) designs. Fujitsu developed its own CPF-based RDF concept for the WiMAX project in 2007. For the main design flow of this project, Fujitsu chose the Cadence Low-Power Solution, which provides full front-to-back low-power capabilities for design, verification, and implementation. The Fujitsu RDF implementation was built around the Cadence platform to ensure smooth integration and data handoffs. Many CPF innovations were also incorporated into the Low-Power Solution and the Cadence Encounter® Digital Implementation System, creating the most advanced turnkey platform for CPF-enabled low-power design.
Operational Impact
  • The adoption of the Cadence Low-Power Solution and the CPF-based RDF concept led to significant improvements in Fujitsu's design process. The unified approach to power design resulted in a significant reduction in leakage power levels and overall chip power consumption. The automated power shutoff (PSO) flow in the Encounter Digital Implementation System also reduced Fujitsu’s physical design turnaround time by about 50%. The CPF-based Cadence Incisive® Design Team Simulator enabled Fujitsu to run logic simulations for the power shutoffs in the design without the need to create a custom programming language interface (PLI). Encounter Conformal® Low Power provided structural and functional verification to identify low-power design rule oversights, contributing to improved quality of silicon (QoS) in the final output. The successful implementation of this project has proven the effectiveness of CPF-enabled techniques in improving performance, increasing productivity, and speeding time to market on real production designs.
Quantitative Benefit
  • Reduced leakage power by 88%
  • Reduced overall power consumption by 36%
  • Reduced physical design turnaround time by 50%

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